Signal processor

ABSTRACT

An object of the present invention is to provide a signal processor which improves the offset accuracy of a video signal without increasing the number of bits of a circuit.  
     An N-bit adder ( 103 ) adds a video signal (S 101 ) and an upper-N-bit signal of a brightness control signal (S 102 ) as an offset value. A 1-bit pulse generator ( 107 ) generates a 1-bit pulse signal (S 107 ) in which “1” and “0” have equal chances of appearing at random. A selector ( 106 ) selects the 1-bit pulse signal (S 107 ) when the LSB of the brightness control signal (S 102 ) is “1”, while selects a ground level “0” when the LSB is “ 0 ”, and supplies the selected signal to a carry input of the N-bit adder ( 103 ).

TECHNICAL FIELD

[0001] The present invention relates to a signal processor and, moreparticularly, to a signal processor which performs brightness adjustmentof video signals.

BACKGROUND ART

[0002] Brightness adjustment of a video signal in a TV receiver or thelike is performed by adding/subtracting an offset signal to/from thevideo signal.

[0003]FIG. 7 is a block diagram illustrating the construction of aconventional signal processor.

[0004] In FIG. 7, the conventional signal processor comprises an N-bitadder 1003 and a controller 1004.

[0005] The N-bit adder 1003 adds an N-bit video signal S1001 inputted toa video signal input terminal 1001 and an N-bit brightness controlsignal S1002 inputted to a brightness control signal input terminal1002, and outputs the addition result from an output 1003D as an N-bitsignal S1003. When overflow occurs, the N-bit adder 1003 outputs anoverflown 1-bit signal, that is, a signal of the most significant bit ofthe N+1 bits as the addition result, from a carry output 1003E as acarry output signal S1004, and outputs a signal of the lower N bits fromthe output 1003D as the N-bit signal S1003. Here, a carry input 1003C ofthe N-bit adder 1003 is grounded.

[0006] The controller 1004 receives the carry output signal S1004 andthe N-bit signal S1003 from the N-bit adder 1003 as input, controls thesignals from the N-bit adder 1003 so that they are equal to or smallerthan a predetermined upper limit and equal to or larger than apredetermined lower limit, and outputs an N-bit signal to a video signaloutput terminal 1005.

[0007] Next, the operation of the conventional signal processor will bedescribed.

[0008] The N-bit video signal S1001 is supplied from the video signalinput terminal 1001 to one input 1003A of the N-bit adder 1003. TheN-bit brightness control signal S1002 is supplied from the brightnesscontrol signal input terminal 1002 to the other input 1003B of the N-bitadder 1003. As the result, a signal obtained by adding the brightnesscontrol signal S1002 to the video signal S1001 is outputted from theoutput 1003D and the carry output 1003E of the N-bit adder.

[0009] The N-bit signal S1003 and the carry output signal S1004 whichare outputted from the N-bit adder 1003 are controlled by the controller1004 so that they are within a range between predetermined values.

[0010] In this way, only an offset-adjusted video signal which isobtained by performing offset adjustment on the video signal S1001 isoutputted from the video signal output terminal 1005.

[0011] However, in the conventional signal processor as described above,the accuracy of offset adjustment is restricted by the number of bits ofthe video signal and the brightness control signal. That is, offsetadjustment of N-bit accuracy is performed in the conventional signalprocessor.

[0012] Thus, in order to improve the accuracy of brightness adjustment,the number of bits of the video signal and the brightness control signalis required to be increased.

[0013] However, when the number of bits is increased, it is required toincrease the number of bits not only in the N-bit adder and thecontroller but also a circuit for processing a signal after offsetadjustment, resulting in an increase in circuit scale.

[0014] The present invention is made to solve the above-describedproblems and has for its object to provide a signal processor which isable to improve the accuracy of brightness adjustment without increasingcircuit scale.

DISCLOSURE OF THE INVENTION

[0015] According to claim 1 of the present invention, there is provideda signal processor comprising: a pulse generator for generating a 1-bitpulse signal having an average logical value of “½”; a selector forselecting either the pulse signal or a signal having a logical value of“0” on the basis of a least-significant-bit signal of an N+1-bit (N isan integral number equal to or larger than “1”) brightness controlsignal; and an N-bit adder for adding an N-bit video signal, anupper-N-bit signal of the N+1-bit brightness control signal, and thesignal selected by the selector.

[0016] According to the present invention, the N-bit adder adds an N-bitvideo signal, an upper-N-bit signal of an N+1-bit brightness controlsignal, and a signal obtained by multiplying the least significant bitof the brightness control signal by ½, which is inputted as carry input,thereby performing brightness adjustment on the N-bit video signal withthe accuracy for N+1 bits, without increasing circuit scale.

[0017] According to claim 2 of the present invention, in the signalprocessor as defined in claim 1, the pulse generator comprises: pluralcounters each of which counts the number of pulses of a periodic signal,and outputs the least significant bit of the counting result; and asingle or plural exclusive OR gates which obtain exclusive OR betweenthe outputs of the plural counters to output as a 1-bit pulse signal.

[0018] According to the present invention, in addition to the sameeffect as achieved by the invention according to claim 1, a 1-bitirregular pulse can be generated by simple construction. Further, apulse signal which has increased random property of a periodic signal isgenerated by the plural counters and a single or plural exclusive ORgates, thereby preventing a patterned picture or the like which could begenerated when a regular pulse signal is employed.

[0019] According to claim 3 of the present invention, in the signalprocessor as defined in claim 1, the pulse generator comprises: a firstcounter which counts the number of pulses of a vertical sync signal, andoutputs the least significant bit of the counting result; a secondcounter which counts the number of pulses of a horizontal sync signal,and outputs the least significant bit of the counting result; a thirdcounter which counts the number of pulses of a pixel clock signal, andoutputs the least significant bit of the counting result; a firstexclusive OR gate which receives either two of the outputs of the firstto third counters, to perform exclusive-OR logic operations; and asecond exclusive OR gate which receives output of one of the first tothird counters, that is not inputted to the first exclusive OR gate, andthe result of the operations by the first exclusive OR gate, to performexclusive-OR logic operations, and outputs the result of the operationsas a 1-bit pulse signal.

[0020] According to the present invention, in addition to the sameeffect as achieved by the invention according to claim 1, a 1-bitirregular pulse can be generated by simple construction. Further, apulse signal which has increased random property of a periodic signal isgenerated by the first to third counters and the first and secondexclusive OR gates, thereby preventing a patterned picture or the likewhich could be generated when a regular pulse signal is employed.

[0021] According to claim 4 of the present invention, there is provideda signal processor comprising: a pulse generator for generating 2^(M)-11-bit pulse signals having average logical values that are equal to orlarger than ½^(M) (M is an integral number equal to or larger than “1”),smaller than “1”, and integral multiples of ½^(M) ; a selector forselecting one of the 2^(M)-1 1-bit pulse signals generated by the pulsegenerator and a signal with a logical value of “0” on the basis of alower-M-bit signal of an N+M-bit (N is an integral number equal to orlarger than “1”) brightness control signal; and an N-bit adder foradding an N-bit video signal, an upper-N-bit signal of the N+M-bitbrightness control signal, and the signal selected by the selector.

[0022] According to the present invention, an upper-N-bit signal of anN+M-bit brightness control signal is added to an N-bit video signal, anda signal obtained by multiplying a lower-M-bit signal of the brightnesscontrol signal by ½^(M) , which is inputted as carry input, is furtheradded thereto, thereby performing brightness adjustment on the N-bitvideo signal with the accuracy for N+M bits, without increasing circuitscale.

[0023] According to claim 5 of the present invention, there is provideda signal processor comprising: a pulse generator for generating three1-bit pulse signals having average logical values of ¾, {fraction (2/4,)} and ¼; a selector for selecting one of the three 1-bit pulse signalsgenerated by the pulse generator and a signal with a logical value of“0” on the basis of a lower-2-bit signal of an N+2-bit (N is an integralnumber equal to or larger than “1”) brightness control signal; and anN-bit adder for adding an N-bit video signal, an upper-N-bit signal ofthe N+2-bit brightness control signal, and the signal selected by theselector.

[0024] According to the present invention, it is possible to performbrightness adjustment on an N-bit video signal with the accuracy for N+2bits, without increasing circuit scale.

[0025] According to claim 6 of the present invention, in the signalprocessor as defined in claim 5, the pulse generator comprises: acounter which counts the number of periodic pulses, and outputs thelower 2 bits of the counting result; and plural logic gates whichperform logical operations on the result of the counting by the counter,and output the three 1-bit pulse signals.

[0026] According to the present invention, in addition to the sameeffect as achieved by the invention according to claim 5, a signalgenerator can be realized with simple construction.

BRIEF DESCRIPTION OF DRAWINGS

[0027]FIG. 1 is a block diagram illustrating the construction of asignal processor according to a first embodiment of the presentinvention.

[0028]FIG. 2 is a block diagram illustrating the construction of asignal processor according to a second embodiment of the presentinvention.

[0029]FIG. 3 is a waveform chart for explaining the operation of thesignal processor according to the second embodiment.

[0030]FIG. 4 is a block diagram illustrating the construction of asignal processor according to a third embodiment of the presentinvention.

[0031]FIG. 5 is a block diagram illustrating the construction of asignal processor according to a fourth embodiment of the presentinvention.

[0032]FIG. 6 is a waveform chart for explaining the operation of thesignal processor according to the fourth embodiment.

[0033]FIG. 7 is a block diagram illustrating the construction of aconventional signal processor.

BEST MODE TO EXECUTE THE INVENTION EMBODIMENT 1

[0034] Hereinafter, a signal processor according to a first embodimentof the present invention will be described with reference to thedrawing.

[0035]FIG. 1 is a block diagram illustrating the construction of thesignal processor according to the first embodiment.

[0036] With reference to FIG. 1, the signal processor according to thefirst embodiment comprises an N-bit adder 103, a controller 104, aselector 106, and a 1-bit pulse generator 107.

[0037] The N-bit adder 103 adds an N-bit video signal S101 supplied toan input 103A, an upper-N-bit signal of an N+1-bit brightness controlsignal S102, which is supplied to an input 103B, and carry inputsupplied to an input 103C. Then, the N-bit adder 103 outputs theaddition result from an output 103D as an N-bit signal S103. Whenoverflow occurs at the addition, the N-bit adder 103 outputs anoverflown 1-bit signal, that is, a signal of the most significant bit ofthe N+1 bits as the addition result, from a carry output 103E as a carryoutput signal S104, and outputs a signal of the lower N bits from theoutput 103D as the N-bit signal S103. Further, N is an integral numberequal to or larger than “1”.

[0038] The controller 104 receives the carry output signal S104 and theN-bit signal S103 from the N-bit adder 103 as input. Then, thecontroller 104 performs control so that the N+1-bit signal which iscomposed of the carry output signal S104 and the N-bit signal S103 iswithin a range between predetermined upper and lower limits and becomesan N-bit signal, and outputs the N-bit signal as the control result to avideo signal output terminal 105.

[0039] The selector 106 selects one of signals inputted to an input 106Aand an input 106B on the basis of a signal inputted to a control input106S, and outputs the selected signal to the N-bit adder 103. Here, theinput 106B of the selector 106 is grounded.

[0040] The 1-bit pulse generator 107 generates a pulse with amplitude“1”, that is, logical value “1”. There is a 50-50 chance that a statewhere the logical value of a pulse signal S107 generated by the 1-bitpulse generator 107 is “0” appears or a state where the logical value is“1” appears. That is, the pulse signal S107 outputted from the 1-bitpulse generator 107 has an average logical value of “0.5”.

[0041] Next, the operation of the signal processor according to thefirst embodiment will be described. In the first embodiment, adescription will be given particularly of a case where a luminancesignal is adjusted.

[0042] The video signal S101 as an N-bit luminance signal is suppliedfrom a video signal input terminal 101 to the input 103A of the N-bitadder 103. The N+1-bit brightness control signal S102 is inputted from abrightness control signal input terminal 102.

[0043] The brightness control signal S102 is divided into a signal ofthe upper N bits and a signal of the least significant bit (LSB), andthe upper-N-bit signal is supplied to the input 103B of the N-bit adder103. On the other hand, the least-significant-bit signal is supplied tothe control input 106S of the selector 106 as a control signal of theselector 106.

[0044] The pulse signal S107 outputted from the 1-bit pulse generator107 is supplied to the input 106A of the selector 106. When a signalwith logical value “1” is supplied to the control input 106S of theselector 106, the selector 106 selects the signal of the input 106A,that is, the pulse signal S107, and outputs the selected signal to theN-bit adder 103. On the other hand, when a signal with logical value “0”is supplied to the control input 106S, the selector 106 selects thesignal of the input 106B, that is, a signal with logical value “0”, andoutputs the selected signal to the N-bit adder 103.

[0045] Accordingly, when the least significant bit of the brightnesscontrol signal S102 is “1”, the output of the selector 106 is “0.5” onaverage. On the other hand, when the least significant bit of thebrightness control signal S102 is “0”, the output of the selector 106 is“0”. That is, average output of the selector 106 has a value obtained bymultiplying the least significant bit of the brightness control signal102S by “0.5”.

[0046] The output from the selector 106 is supplied to the input 103C ofthe N-bit adder 103. Then, the N-bit adder 103 adds the N-bit videosignal S101 supplied to the input 103A, the upper-N-bit signal of theN+1-bit brightness control signal S102, which is supplied to the input103B, and the 1-bit carry input supplied to the input 103C. At theaddition in the N-bit adder 103, the 1-bit carry input supplied to theinput 103C is added for the least significant bit.

[0047] When the brightness control signal S102 has a negative value, thebrightness control signal S102 is added to the video signal S101, whichresults in the video signal S101 from which offset is subtracted.

[0048] Then, when the addition result is N bits, the N-bit adder 103outputs the addition result from the output 103D as the N-bit signalS103. On the other hand, when the addition result is N+1 bits, the N-bitadder 103 outputs an overflown 1-bit signal, that is, a signal of themost significant bit of the addition result, from the output 103E as thecarry output signal S104, and outputs a signal of the lower N bits fromthe output 103D as the N-bit signal S103.

[0049] When the controller 104 receives the N-bit signal S103 and thecarry output signal S104 from the N-bit adder 103, the controller 104performs control so that the N+1-bit signal composed of both of theabove-described signals is within a range between predetermined upperand lower limits and becomes an N-bit signal. Then, the controller 104outputs an N-bit offset-adjusted video signal as the control result to avideo signal output terminal 105.

[0050] Though this offset-adjusted video signal is composed of N bits,it is obtained by performing brightness adjustment with the accuracy forN+1 bits. A description will be briefly given of the accuracy ofbrightness adjustment.

[0051] When the least significant bit of the brightness control signalS102 is “1”, a signal of averaging “0.5” is inputted to the carry input103C of the N-bit adder 103. For example, when a value of a signalobtained by adding the video signal S101 and the brightness controlsignal S102 is “10” in decimal, there is an equal chance that the outputof the N-bit adder 103 is “10” or “11”. Accordingly, the output of theN-bit adder 103 can be supposedly “10.5”. That is, gradation of thevideo signal can be adjusted in 0.5 unit, so that the gradation becomestwice as high on the whole, resulting in accuracy improved by 1 bit.

[0052] As described above, according to the signal processor of thefirst embodiment, the N-bit adder 103 adds the N-bit video signal S101and the upper-N-bit signal of the N+1-bit brightness control signalS102, and further adds, thereto, a signal obtained by multiplying theleast-significant-bit signal of the brightness control signal S102 by“0.5”, which is inputted as carry input, thereby performing brightnessadjustment on the N-bit video signal S101 with the accuracy for N+1bits, without increasing circuit scale.

[0053] While in the first embodiment the description has been given ofthe case where the output from the selector 106 is added at the N-bitadder 103 as carry input, the N-bit adder according to the presentinvention may be a 3-input adder or the like, which adds the signal fromthe selector 106, the N-bit video signal S101, and the upper-N-bitsignal of the brightness control signal S102.

[0054] The 1-bit pulse generator 107 according to the first embodimentmay generate either a periodic pulse signal or an irregular, notperiodic, pulse signal.

[0055] Further, while in the first embodiment the video signal S101 is aluminance signal, the video signal according to the present inventionmay be other signals than the luminance signal.

EMBODIMENT 2

[0056] Hereinafter, a signal processor according to a second embodimentof the present invention will be described with reference to thedrawings. The signal processor according to the second embodiment is onefor showing an example of the 1-bit pulse generator 107 of the firstembodiment, in which a vertical sync signal, a horizontal sync signal,and a pixel clock signal are used to generate a 1-bit pulse signal.

[0057]FIG. 2 is a block diagram illustrating the construction of thesignal processor according to the second embodiment.

[0058] With reference to FIG. 2, the signal processor according to thesecond embodiment comprises an N-bit adder 103, a controller 104, aselector 106, 1-bit counters 111, 112, and 113, and exclusive OR gates114A and 114B. The constructions and operations of the N-bit adder 103,the controller 104, and the selector 106 are the same as those describedfor the first embodiment, and descriptions thereof will be omitted.

[0059] The 1-bit counter 111 receives a vertical sync signal S108 asinput, counts the number of times that a vertical sync pulse issupplied, and outputs a signal of the least significant bit of thecounting result as a 1-bit output signal S111. That is, the 1-bitcounter 111 outputs the 1-bit output signal S111 in which “0” and “1”are alternately repeated every time the vertical sync pulse of thevertical sync signal S108 is inputted.

[0060] In the same way as the 1-bit counter 111, the 1-bit counters 112and 113 receive a horizontal sync signal S109 and a pixel clock signalS110, respectively, as input, count the number of times that a verticalsync pulse and a pixel clock pulse are supplied, and output signals ofthe least significant bits of the counting results as 1-bit outputs S112and S113.

[0061] Next, the operation of the signal processor according to thesecond embodiment will be described.

[0062] Initially, the vertical sync signal S108 is supplied from avertical sync signal input terminal 108 to the 1-bit counter 111. Then,the 1-bit output signal S111 is outputted from the 1-bit counter 111.

[0063] Likewise, the horizontal sync signal S109 and the pixel clocksignal S110 are supplied from a horizontal sync signal input terminal109 and a pixel clock signal input terminal 110 to the 1-bit counters112 and 113, respectively, and the 1-bit output signals S112 and S113are outputted from the 1-bit counters 112 and 113.

[0064] The three 1-bit output signals S111, S112, and S113 outputtedfrom the three 1-bit counters 111, 112, and 113 are subjected to logicaloperations by the two exclusive OR gates 114A and 114B, and a signalobtained by the logical operations is supplied to the input terminal106A of the selector 106. The logical operations here are performed asfollows: an exclusive OR between the two 1-bit output signals S111 andS112 is initially obtained by the exclusive OR gate 114A, and anexclusive OR between an output signal of the exclusive OR gate 114A andthe 1-bit output signal S113 is further obtained by the exclusive ORgate 114B.

[0065] A 1-bit pulse signal S114 outputted from the exclusive OR gate114B is supplied to the input 106A of the selector 106. The operationhereafter is the same as that described for the first embodiment, and adescription thereof will be omitted.

[0066]FIG. 3 is a waveform chart illustrating variations of therespective signals of the signal processor according to the secondembodiment.

[0067] As shown in FIG. 3, in the 1-bit output signals S111, S112, andS113 which are obtained by counting the pulses of the vertical syncsignal S108, the horizontal sync signal S109, and the pixel clock signalS110, respectively, states where a logical value is “1” and where thelogical value is “0” alternately and periodically appear. Thus, it ispossible to consider that each of the 1-bit counters 111, 112, and 113outputs a signal with average logical value of “0.5”. Further, byperforming the above-described logical operations employing exclusive ORon the 1-bit output signals S111, S112, and S113, irregular property isadded to the appearance of “1” and “0”. Accordingly, the 1-bit pulsesignal S114 outputted from the exclusive OR gate 114B is an irregularpulse signal. When this signal S114 is treated as output of the 1-bitpulse generator 107 of the first embodiment, also in this secondembodiment, offset adjustment of the video signal S101 can be performedwith the accuracy for N+1 bits as in the first embodiment.

[0068] As described above, the signal processor according to the secondembodiment are provided with the 1-bit counters 111, 112, and 113, whichcount pulses of the vertical sync signal S108, the horizontal syncsignal S109, and the pixel clock signal S110, respectively, and theexclusive OR gates 114 A and 114B which perform logical operations onthe outputs of the 1-bit counters 111, 112, and 113, so as to output the1-bit pulse signal S114. Therefore, in addition to the same effect asachieved by the first embodiment, the 1-bit pulse signal S114 can begenerated by a simple construction.

[0069] Further, the 1-bit pulse signal S114 which has increased therandom property of the periodic signal is generated by the 1-bitcounters 111, 112, and 113, and the exclusive OR gates 114A and 114B,thereby preventing a patterned picture or the like which could begenerated when a regular 1-bit pulse signal is employed.

[0070] While in the second embodiment, among the three 1-bit outputsignals S111, S112, and S113, the two 1-bit output signals S111 and S112are inputted to the exclusive OR gate 114A, and the other 1-bit outputsignal S113 is inputted to the exclusive OR gate 114B, the combinationof the two 1-bit output signals to be inputted to the exclusive OR gate114A and the other 1-bit output signal to be inputted to the exclusiveOR gate 114B, among the three 1-bit output signals S111, S112, and S113is not restricted to that described in the second embodiment.

[0071] Further, while in the second embodiment the three 1-bit countersare provided, the number of 1-bit counters is not restricted to three.For example, one, two, four or more 1-bit counters may be provided. Whenfour 1-bit counters are provided, there are provided a first exclusiveOR gate which obtains an exclusive OR between outputs from either two ofthe four 1-bit counters, a second exclusive OR gate which obtains anexclusive OR between the exclusive OR obtained by the first exclusive ORgate and output from another 1-bit counter, and a third exclusive ORgate which obtains an exclusive OR between the exclusive OR obtained bythe second exclusive OR gate and output from the remaining 1-bitcounter, and output of the third exclusive OR gate is regarded as the1-bit pulse signal S114.

[0072] Or, there may be provided a first exclusive OR gate which obtainsan exclusive OR between outputs of either two of the four 1-bitcounters, a second exclusive OR gate which obtains an exclusive ORbetween outputs of the other two 1-bit counters, and a third exclusiveOR gate which obtains an exclusive OR between outputs of both of thefirst and second exclusive OR gates, and output of the third exclusiveOR gate is regarded as the 1-bit pulse signal S114.

[0073] Further, in the second embodiment the three signals, the verticalsync signal S108, the horizontal sync signal S109, and the pixel clocksignal S110 are used to generate the 1-bit pulse signal S114. However,even when at least one of the three signals is used, and a signalobtained by performing counting on the above-described signal with the1-bit counter is supplied to the input 106A of the selector 106, asignal obtained by multiplying the least-significant-bit signal of thebrightness control signal S102 by “0.5” is supplied to the carry inputof the N-bit adder 103, thereby enabling offset adjustment of the videosignal S101 with the accuracy for N+1 bits.

[0074] Furthermore, while in the second embodiment the signals inputtedto the 1-bit counters 111, 112, and 113 are the vertical sync signalS108, the horizontal sync signal S109, and the pixel clock signal S110,they may be other periodic signals than described above.

EMBODIMENT 3

[0075] Hereinafter, a signal processor according to a third embodimentof the present invention will be described with reference to thedrawing.

[0076]FIG. 4 is a block diagram illustrating the construction of thesignal processor according to the third embodiment.

[0077] With reference to FIG. 4, the signal processor according to thethird embodiment comprises an N-bit adder 103, a controller 104, aselector 115, and a pulse generator 116. The constructions andoperations of the N-bit adder 103 and the controller 104 are the same asthose described for the first embodiment, and descriptions thereof willbe omitted.

[0078] The selector 115 selects one from 2^(M) input signals on thebasis of an M-bit control signal, and outputs the selected signal to theN-bit adder 103. Here, one of inputs of the selector 115 is grounded.Further, M is an integral number equal to or larger than “1”.

[0079] The pulse generator 116 generates all pulse signals havinglogical values which become “1” in an arbitrary period at the rate of½^(M) and more, (2^(M)−1)/2^(M) and less, and ½^(M) and its integralmultiples, and outputs the generated pulse signals to the selector 115.The pulse signal having a logical value which becomes “1” in anarbitrary period at the rate of ½^(M) is regarded as a signal with anaverage logical value “½^(M) ”. The pulse signal having a logical valuewhich becomes “1” in an arbitrary period at the rate L times as high as½^(M) is regarded as a signal with an average logical value “L/2^(M)”.Accordingly, it is regarded that the pulse generator 116 outputs2^(M)-1, in total, pulse signals having average logical values equal toor larger than ½^(M) and smaller than “1”, in ½^(M) unit, to supply tothe selector 115. Further, since one of the input terminals of theselector 115 is grounded, it is regarded that 2^(M) signals havingaverage logical values that are equal to or larger than “0”, smallerthan “1”, and integral multiples of ½^(M) are supplied to the selector115.

[0080] Next, the operation of the signal processor according to thethird embodiment will be described.

[0081] Initially, an N-bit video signal S101 is supplied from a videosignal input terminal 101 to the input 103A of the N-bit adder 103. AnN+M-bit brightness control signal S102 is inputted from a brightnesscontrol signal input terminal 102.

[0082] The brightness control signal S102 is divided into a signal ofthe upper N bits and a signal of the lower M bits, and the upper-N-bitsignal is supplied to the input 103B of the N-bit adder 103. On theother hand, the lower-M-bit signal is supplied to the control input 115Sof the selector 115 as a control signal of the selector 115.

[0083] The 2^(M)−1 pulse signals outputted from the pulse generator 116are supplied to the selector 115. The control signal as the lower-M-bitsignal of the brightness control signal S102 has an integral valueranging from “0” to “2^(M)−1” in decimal expression. When the decimalexpression of this control signal is K, the selector 115 selects asignal having an average logical value K times as large as ½^(M) , fromthe inputs from the pulse generator 116 and from the grounded input, andoutputs the selected signal to the carry input 103C of the N-bit adder103. Thus, the carry input 103C of the N-bit adder 106 is supplied witha signal obtained by multiplying the lower-M-bit signal of thebrightness control signal S102 by ½^(M). The operation hereafter is thesame as that described for the first embodiment, and a descriptionthereof will be omitted.

[0084] As described above, according to the signal processor of thethird embodiment, an upper-N-bit signal of the N+M-bit brightnesscontrol signal S102 is added to the N-bit video signal S101, and asignal obtained by multiplying a lower-M-bit signal of the brightnesscontrol signal S102 by ½^(M), which is inputted as carry input, isfurther added thereto, thereby performing brightness adjustment on theN-bit video signal S101 with the accuracy for N+M bits, withoutincreasing circuit scale.

[0085] The 2^(M)−1 pulse signals generated by the pulse generator 116according to the third embodiment may be either periodic pulse signalsor irregular, not periodic, pulse signals.

EMBODIMENT 4

[0086] Hereinafter, a signal processor according to a fourth embodimentof the present invention will be described with reference to thedrawings. The signal processor according to the fourth embodiment is onefor showing an example where a value of M in the third embodiment is“2”, and is provided with a 2-bit counter and logic gates as the pulsegenerator 116.

[0087]FIG. 5 is a block diagram illustrating the construction of thesignal processor according to the fourth embodiment.

[0088] With reference to FIG. 5, the signal processor according to thefourth embodiment comprises an N-bit adder 103, a controller 104, a2-bit counter 118, logical negation gates 119 and 120, AND gates 121 and122, an OR gate 123, and a selector 124. The constructions andoperations of the N-bit adder 103 and the controller 104 are the same asthose described for the first embodiment, and descriptions thereof willbe omitted.

[0089] The 2-bit counter 118 receives a pulse signal S117 as input,counts the number of times that the pulse signal S117 changes to “1”,and outputs the lower 2 bits of this counted value (hereinafter,referred to as a “counted value”). That is, the 2-bit counter 118repeatedly and sequentially outputs four kinds of counted values, “0”,“1”, “2”, and “3”.

[0090] The selector 124 selects one of signals inputted to inputs 124A,124B, 124C, and 124D by a 2-bit signal inputted to a control terminal124S, and outputs the selected signal to the N-bit adder 103.

[0091] Next, the operation of the signal processor of the fourthembodiment will be described.

[0092] Initially, the pulse signal S117 is supplied from a pulse signalinput terminal 117 to the 2-bit counter 118. Then, a counted value isoutputted from the 2-bit counter 118. Of the 2 bits of counted value,the upper bit is outputted from an output 118A and the lower bit isoutputted from an output 118B. Here, as the pulse signal S117, aperiodic pulse signal such as the vertical sync signal, the horizontalsync signal, and the pixel clock signal as described in the secondembodiment is employed.

[0093] The counted value is subjected to logical operations by the logicgates 119 to 123, and signals obtained as the results of logicaloperations, S124A, S124B, and S124C are supplied to input terminals124A, 124B, and 124C of the selector 124, respectively.

[0094] To be specific, the signal from the output 118A of the 2-bitcounter 118 is inverted by the logical negation gate 120, and theinverted signal is inputted to the AND gates 121 and 122. The signalfrom the output 118B is inputted to the AND gate 122. Further, a signalobtained by inverting the signal from the output 118B with the logicalnegation gate 119 is inputted to the AND gate 121 and the OR gate 123,and is further supplied to the input 124B of the selector 124 as thesignal S124B. An AND obtained by the AND gate 121 is inputted to theinput 124C of the selector 124 as the signal S124C. An AND obtained bythe AND gate 122 is inputted to the OR gate 123, and an OR obtained bythe OR gate 123 is inputted to the input 124A of the selector 124 as thesignal S124A.

[0095]FIG. 6 is a waveform chart illustrating variations of therespective signals of the signal processor according to the fourthembodiment.

[0096] As shown in FIG. 6, the 2-bit counter 118 outputs a counted valueobtained by counting the number of times that the pulse signal S117changes to “1”. The signals S124A, S124B, and S124C obtained as theresults of logical operations by the logic gates 119 to 123, which aresupplied to the input terminals 124A, 124B, and 124C vary as shown inFIG. 6. That is, a logical value of the signal S124A becomes “1” whenthe counted value is other than “3”, a logical value of the signal S124Bbecomes “1” when the counted value is “0”or “2”, and a logical value ofthe signal S124C becomes “1” only when the counted value is “0”.

[0097] As described above, the counted value has four kinds of values,each having ¼ chance of appearing. When attention is focused on therespective signals supplied to the selector 124, for example, thelogical value of the signal S124C becomes “1” at the time of one countedvalue among the four counted values. That is, a period during which thelogical value of the signal S124C is “1” corresponds to a quarter of thetotal. Thus, the signal S124C is regarded to have an average logicalvalue of “0.25”.

[0098] Likewise, the logical value of the signal S124B becomes “1” intwo-fourths of the whole period, and thus the signal S124B is regardedto have an average logical value of “0.5”. The logical value of thesignal S124A becomes “1” in three-fourths of the whole period, and thusthe signal S124A is regarded to have an average logical value of “0.75”.

[0099] Since the remaining input terminal 124D of the selector 124 isgrounded, the selector 124 receives the four signals having the averagelogical values of “0”, “0.25”, “0.5”, and “0.75”, selects either one ofthese signals by a control signal, and supplies the selected signal tothe carry input 103C of the N-bit adder 103.

[0100] As described above, a lower-2-bit signal of an M+2-bit brightnesscontrol signal S102 is supplied as the control signal of the selector124, and this 2-bit signal indicates values “0” to “3”. When the valueis “0”, “1”, “2”, or “3”, the selector 124 selects and outputs thesignal having the average logical value of “0”, “0.25”, “0.5”, or“0.75”, respectively. Therefore, the carry input 103C of the N-bit adder103 is supplied with a signal having a value obtained by multiplying thelower 2 bits of the brightness control signal S102 by “0.25”. Theoperation hereafter is the same as that described for the firstembodiment, and a description there of will be omitted.

[0101] As described above, according to the signal processor of thefourth embodiment, the upper-N-bit signal of the N+2-bit brightnesscontrol signal S102 is added to the N-bit video signal S101, and asignal obtained by multiplying a lower-2-bit signal of the brightnesscontrol signal S102 by “0.25”, which is inputted as carry input, isfurther added thereto, thereby performing brightness adjustment on theN-bit video signal S101 with the accuracy for N+2 bits, withoutincreasing circuit scale.

[0102] Further, the 2-bit counter 118 which counts a pulse of the pulsesignal S117 to output a 2-bit counted value, and the logic gates 119 to123 which performs logical operations on the 2-bit counted value tosupply the signals S124A, S124B, and S124C to the selector 124 areprovided, thereby realizing the pulse generator 116 of the thirdembodiment with simple construction.

[0103] While in the above-described respective embodiments, in thesignal processor according to the present invention, the controller 104places restrictions on the output from the N-bit adder 103, the signalprocessor according to the present invention does not need to have thecontroller 104 when the offset-adjusted video signal may be an N+1-bitsignal. In this case, the N+1-bit signal composed of the N-bit signalS103 from the N-bit adder 103 and the 1-bit carry output signal S104 isan offset-adjusted video signal.

APPLICABILITY IN INDUSTRY

[0104] As described above, a signal processor according to the presentinvention is suited for a signal processor which performs brightnessadjustment of a video signal by adding a brightness control signal as anoffset value to the video signal.

1. A signal processor comprising: a pulse generator for generating a1-bit pulse signal having an average logical value of “½”; a selectorfor selecting either the pulse signal or a signal having a logical valueof “0” on the basis of a least-significant-bit signal of an N+1-bit (Nis an integral number equal to or larger than “1”) brightness controlsignal; and an N-bit adder for adding an N-bit video signal, anupper-N-bit signal of the N+1-bit brightness control signal, and thesignal selected by the selector.
 2. The signal processor as defined inclaim 1, wherein the pulse generator comprises: plural counters each ofwhich counts the number of pulses of a periodic signal, and outputs theleast significant bit of the counting result; and a single or pluralexclusive OR gates which obtain exclusive OR between the outputs of theplural counters to output as a 1-bit pulse signal.
 3. The signalprocessor as defined in claim 1, wherein the pulse generator comprises:a first counter which counts the number of pulses of a vertical syncsignal, and outputs the least significant bit of the counting result; asecond counter which counts the number of pulses of a horizontal syncsignal, and outputs the least significant bit of the counting result; athird counter which counts the number of pulses of a pixel clock signal,and outputs the least significant bit of the counting result; a firstexclusive OR gate which receives either two of the outputs of the firstto third counters, to perform exclusive-OR logic operations; and asecond exclusive OR gate which receives output of one of the first tothird counters, that is not inputted to the first exclusive OR gate, andthe result of the operations by the first exclusive OR gate, to performexclusive-OR logic operations, and outputs the result of the operationsas a 1-bit pulse signal.
 4. A signal processor comprising: a pulsegenerator for generating 2^(M)−1 1-bit pulse signals having averagelogical values that are equal to or larger than ½^(M) (M is an integralnumber equal to or larger than “1”), smaller than “1”, and integralmultiples of ½^(M); a selector for selecting one of the 2^(M)−1 1-bitpulse signals generated by the pulse generator and a signal with alogical value of “0” on the basis of a lower-M-bit signal of an N+M-bit